This application relates to interconnection structures especially useful in semiconductor devices such as integrated circuits and memory devices and relates to methods for fabricating and using such structures.
Integrated circuits including arrays of memory nodes or logic gates have increased steadily in density. Such integrated circuits have included dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, programmable read-only memory (PROM) integrated circuits, electrically erasable programmable read-only memory (EEPROM) integrated circuits, write-once read-many (WORM) memory devices, and logic devices such as programmable logic array (PLA) integrated circuits, among others. Integrated circuits having arrays of devices, gates, or memory nodes disposed on multiple levels require xe2x80x9cverticalxe2x80x9d interconnections or xe2x80x9cpillarsxe2x80x9d to interconnect devices, gates, or memory nodes on one level with other devices, gates, or nodes on other levels. In this context, the term xe2x80x9cverticalxe2x80x9d differs from its everyday connotation in that it does not refer to the direction of gravity. Throughout this specification, the drawings, and the appended claims, the term xe2x80x9cverticalxe2x80x9d refers to a direction generally perpendicular to a substrate or base plane of an integrated circuit. Also, the term xe2x80x9cpillarxe2x80x9d referring to an interconnection and the term xe2x80x9cvertical interconnectionxe2x80x9d are used interchangeably to mean an interconnection communicating between different layers of an integrated circuit, regardless of the spatial orientation of those different layers. Integrated circuits herein include not only monolithic integrated circuits, but also hybrid integrated circuits and multi-layer or xe2x80x9cstackedxe2x80x9d modules. The term xe2x80x9ccellxe2x80x9d herein refers to a functional element of an array, such as a memory node, a logic gate, a switching device, a field-effect device, or a semiconductor device.
There is a continuing need for increased device density in integrated circuits, including multi-layer integrated circuits and for efficient interconnection structures within such multi-layer integrated circuits.